The present disclosure relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, manufacturing method of a semiconductor device, a semiconductor device, and an electronic device.
An electronic device such as a digital video camera, digital still camera, and the like include a semiconductor device such as a solid-state imaging device. For example, a solid-state imaging device includes a CMOS (Complementary Metal Oxide Semiconductor)-type image sensor and CCD (Charge Coupled Device)-type image sensor.
A solid-state imaging device has multiple pixels arrayed on a face of a semiconductor substrate. A photoelectric converter is provided to each pixel. The photoelectric converter is a photodiode, for example, and generates signal load by receiving the incident light via an external optical system with a light-receiving face and performing photoelectric conversion.
With the solid-state imaging device, generally, the photoelectric converter receives incident light at a front face side on which a circuit or wiring has been provided to the semiconductor substrate. In such a case, the circuit and wiring blocks the incident light, and accordingly there are cases wherein improving sensitivity is difficult. Therefore, a “rear projection type” has been proposed, wherein the photoelectric converter receives the incident light at a rear side which is on the opposite side from the front face on which the circuit and wiring has been provided to the semiconductor substrate (e.g., reference Japanese Unexamined Patent Application Publication No. 2005-150463 and Japanese Unexamined Patent Application Publication No. 2008-182142).
Also, with a semiconductor device such as the solid-state imaging device described above, “three-dimensional packaging” has been proposed, wherein multiple substrates, on which devices with differing functions have been provided, are layered and electrically connected to one another. With “three-dimensional packaging”, an optimal circuit corresponding to each function is formed on each substrate, whereby improving the device function can be readily realized. For example, a sensor substrate on which a sensor device is provided and a logic substrate on which a logic circuit for processing signals output from the sensor device thereof are layered to configure a solid-state imaging device. Now, a pad opening is provided by perforating the semiconductor substrate so that the front face of the pad wiring is exposed, and by filling conductive material in the pad opening thereof, the devices are electrically connected with one another. That is to say, the sensor substrate and logic substrate are electrically connected to each other via TSV (Through Silicon Via) (e.g., Japanese Unexamined Patent Application Publication No. 2010-245506).
Further, U.S. Pat. No. 4,349,232 discloses a solid-state imaging device wherein a signal processing chip is layered onto a sensor chip, and Japanese Unexamined Patent Application Publication No. 2008-182142 discloses a technique to electrically connect a sensor chip in a semi-manufactured state and a signal processing chip in a semi-manufactured state to have a completed product.